In silicon semiconductor device fabrication, chemical removal of polysilicon or amorphous silicon and silicon nitride layers can be performed using both wet and dry etching techniques. Dry etching is especially well-suited for precise linewidth and profile control in Very Large Scale Integrated Circuit (VLSI) processing and nanostructure fabrication. However, wet etching still plays an important role where linesize or profile control is not critical, or where the removal of a blanket film is required. For such applications, wet etching can offer advantages of high etch rate combined with high selectivity to dissimilar material layers, while avoiding the problem of plasma or radiation damage that may be present in dry etching techniques.
In silicon metal-oxide semiconductor (MOS) integrated circuit (IC) fabrication, polysilicon is used at different levels such as gate and interconnect. It is also used as a buffer layer for stress relief during the poly-buffered local oxidation of silicon (PBL) process. The PBL process is used at an early stage of silicon device fabrication to form silicon oxide regions which can act as isolation oxide. Briefly, the PBL process proceeds as follows. After a thin oxide layer is formed over a silicon substrate, a polysilicon layer is deposited, followed by a silicon nitride layer. The combined nitride and polysilicon layers, sometimes referred to as a nitride/poly stack, are then patterned using photolithography and etching techniques which are well known in the semiconductor industry. With the patterned nitride/poly stack acting as a mask, oxidation is performed to produce field oxide regions over the silicon substrate. This nitride/poly stack generally needs to be removed prior to subsequent processing. Existing techniques employ either a combination of wet and dry etching, or wet etching alone. In the wet/dry combination, for example, silicon nitride can be removed in a hot acid bath followed by dry etching of the polysilicon layer. Typical plasma etching, however, may cause damage to the underlying oxide and substrate. Such damage can be minimized by wet etching to remove both nitride and polysilicon layers.
In an existing PBL process, a 2-step procedure can be used for the removal of the nitride/poly stack. Hot phosphoric acid (H.sub.3 PO.sub.4) may be used for removing the nitride layer, followed by dry etching of polysilicon. Alternatively, the polysilicon may be removed by using a phosphoric and nitric acid mixture (H.sub.3 PO.sub.4 /HNO.sub.3).
Those skilled in the semiconductor art often try to simplify existing processing steps. An alternative to the process described above may be a one-step procedure for removing the nitride and silicon etch control without sacrificing the high selectivity to dissimilar materials, such as silicon oxide.
Many different liquid etchants have been used in the field of IC processing. Hydrofluoric acid (HF), nitric acid (HNO.sub.3), or potassium hydroxide (KOH) are such examples, but their oxide etch rates may be too high for certain applications.
Other variations include the MEMC J. Electrochem. Soc.: Solid-State Sci. and Tech., p. 945, March 1990! and Wright-Jenkins J. Electrochem. Soc.: Solid-State Sci. and Tech., p. 757, May 1977! formulations, where copper is added as a catalyst to different acid mixtures. The MEMC etch is used for the characterization of silicon defects. It contains copper nitrate (Cu(NO.sub.3).sub.2) in an aqueous mixture of HF,HNO.sub.3 and acetic acid (CH.sub.3 COOH). The Wright-Jenkins mixture shows a preferential etch for (100)- and (111)-oriented, p- and n-doped silicon. It contains chromic oxide (CrO.sub.3), in addition to HF,HNO.sub.3, CH.sub.3 COOH, H.sub.2 O and Cu(NO.sub.3)NO.sub.3